Energy-Saving Write/Read Operation of Memory Cell by Using Separated Storage Device and Remote Reading With an MIS Tunnel Diode Sensor

An efficient way to reduce the loss of stored charge in a memory cell was proposed in this paper. Conventionally, the storage structure is stressed by applying voltages during the read operation. By structurally separating the read operation from the storage structure, lower disturbance to the stored charge can be expected. The metal-insulator-semiconductor (MIS) tunnel diode (TD) sensor was the proposed device for the read operation. The saturation current of the MIS TD can be exponentially affected by the remote stored charge. By comparing the write and read operations of the proposed memory cell with the conventional flash memory cell, it is believed that the proposed cell needs lower voltage to be applied within a read/write cycle, i.e., more energy-saving than the conventional cell.

[1]  C. Faulkner,et al.  A new route to zero-barrier metal source/drain MOSFETs , 2004, IEEE Transactions on Nanotechnology.

[2]  Role of Lateral Diffusion Current in Perimeter-Dependent Current of MOS(p) Tunneling Temperature Sensors , 2014, IEEE Transactions on Electron Devices.

[3]  J. Hwu,et al.  Comprehensive study on the deep depletion capacitance-voltage behavior for metal-oxide-semiconductor capacitor with ultrathin oxides , 2009 .

[4]  Y. Nishi,et al.  Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET , 2008, 2008 Symposium on VLSI Technology.

[5]  Meng Chuan Lee,et al.  Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices , 2013, IEEE Transactions on Electron Devices.

[6]  Photosensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode , 2014, IEEE Transactions on Electron Devices.

[7]  S. Mohney,et al.  Barrier height reduction to 0.15eV and contact resistivity reduction to 9.1×10−9 Ω-cm2 using ultrathin TiO2−x interlayer between metal and silicon , 2013, Symposium on VLSI Technology.

[8]  Contact resistance reduction to FinFET source/drain using dielectric dipole mitigated Schottky barrier height tuning , 2010, 2010 International Electron Devices Meeting.

[9]  T. Hamamoto,et al.  On the retention time distribution of dynamic random access memory (DRAM) , 1998 .

[10]  Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS Gated-MIS Tunnel Transistor , 2015, IEEE Transactions on Electron Devices.

[11]  G. C. Jain,et al.  On the Mechanism of the Anodic Oxidation of Si at Constant Voltage , 1979 .