Programming scheme based optimization of hybrid 4T-2R OxRAM NVSRAM

In this paper, we present a novel single-cycle programming scheme for 4T-2R NVSRAM, exploiting pulse engineered input signals. OxRAM devices based on 3 nm thick bi-layer active switching oxide and 90 nm CMOS technology node were used for all simulations. The cell design is implemented for real-time non-volatility rather than last-bit, or power-down non-volatility. Detailed analysis of the proposed single-cycle, parallel RRAM device programming scheme is presented in comparison to the two-cycle sequential RRAM programming used for similar 4T-2R NVSRAM bit-cells. The proposed single-cycle programming scheme coupled with the 4T-2R architecture leads to several benefits such as- possibility of unconventional transistor sizing, 50% lower latency, 20% improvement in SNM and ~20× reduced energy requirements, when compared against two-cycle programming approach.

[1]  Naoki Kasai,et al.  Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs , 2009, IEEE J. Solid State Circuits.

[2]  S. Takahashi,et al.  A 128 kb FeRAM macro for a contact/contactless smart card microcontroller , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[3]  E. Vianello,et al.  HfO2-Based OxRAM Devices as Synapses for Convolutional Neural Networks , 2015, IEEE Transactions on Electron Devices.

[4]  M. Takata,et al.  Nonvolatile SRAM based on Phase Change , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[5]  Chaitali Chakrabarti,et al.  A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Fabrizio Lombardi,et al.  Designs of PMC-based non-volatile memory circuits for data restoring , 2016, 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO).

[7]  N. Takai,et al.  Sawtooth generator using two triangular waves , 2008, 2008 51st Midwest Symposium on Circuits and Systems.

[8]  Elisa Vianello,et al.  On the forming-free operation of HfOx based RRAM devices: Experiments and ab initio calculations , 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[9]  Chuan Zhang,et al.  A Reconfigurable Smart Sensor Interface for Industrial WSN in IoT Environment , 2014, IEEE Transactions on Industrial Informatics.

[10]  N. Xu,et al.  Characteristics and mechanism of conduction/set process in TiN∕ZnO∕Pt resistance switching random-access memories , 2008 .

[11]  O. Richard,et al.  10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation , 2011, 2011 International Electron Devices Meeting.

[12]  Yue-Der Chih,et al.  Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[13]  L. Goux,et al.  Improvement of data retention in HfO2/Hf 1T1R RRAM cell under low operating current , 2013, 2013 IEEE International Electron Devices Meeting.

[14]  Meng-Fan Chang,et al.  A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[15]  Jagan Singh Meena,et al.  Overview of emerging nonvolatile memory technologies , 2014, Nanoscale Research Letters.

[16]  H. Ahn,et al.  Realization of vertical resistive memory (VRRAM) using cost effective 3D process , 2011, 2011 International Electron Devices Meeting.

[17]  Tetsuo Endoh,et al.  Studies on Static Noise Margin and Scalability for Low-Power and High-Density Nonvolatile SRAM using Spin-Transfer-Torque (STT) MTJs , 2011 .

[18]  Daniele Ielmini,et al.  Resistive switching memories based on metal oxides: mechanisms, reliability and scaling , 2016 .

[19]  Ari Paasio,et al.  Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

[20]  Frederick T. Chen,et al.  Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance , 2010, 2010 International Electron Devices Meeting.

[21]  Valeriu Beiu,et al.  Ultra-low power SRAM cells with unconventional sizing , 2014, 14th IEEE International Conference on Nanotechnology.

[22]  Luca Larcher,et al.  Bipolar Resistive RAM Based on ${\rm HfO}_{2}$: Physics, Compact Modeling, and Variability Control , 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[23]  B. Delley,et al.  Role of Oxygen Vacancies in Cr‐Doped SrTiO3 for Resistance‐Change Memory , 2007, 0707.0563.

[24]  Manan Suri,et al.  Stability analysis of hybrid CMOS-RRAM based 4T-2R NVSRAM , 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).

[25]  Meng-Fan Chang,et al.  Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications , 2012, IEEE Journal of Solid-State Circuits.

[26]  Shoji Ikeda,et al.  High-density and low-power nonvolatile static random access memory using spin-transfer-torque magnetic tunnel junction , 2012 .

[27]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.

[28]  Fabrizio Lombardi,et al.  Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation , 2014, IEEE Transactions on Nanotechnology.

[29]  Frederick T. Chen,et al.  Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

[30]  In Jae Chung,et al.  Comprehensive Electromagnetic Modeling of On-Chip Switching Noise Generation and Coupling , 2008, IEEE Transactions on Advanced Packaging.

[31]  Shimeng Yu,et al.  HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. , 2013, ACS nano.

[32]  Yu Jiang,et al.  Effect of the programming pulse width on resistive memory switching behavior , 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

[33]  D. Gilmer,et al.  Controlling uniformity of RRAM characteristics through the forming process , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[34]  L. Goux,et al.  Understanding of the endurance failure in scaled HfO2-based 1T1R RRAM through vacancy mobility degradation , 2012, 2012 International Electron Devices Meeting.

[35]  Manan Suri,et al.  Hybrid CMOS-OxRAM based 4T-2R NVSRAM with efficient programming scheme , 2016, 2016 16th Non-Volatile Memory Technology Symposium (NVMTS).

[36]  H. Ohno,et al.  A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme , 2013, IEEE Journal of Solid-State Circuits.

[37]  Yuan Xie,et al.  Modeling, Architecture, and Applications for Emerging Memory Technologies , 2011, IEEE Design & Test of Computers.

[38]  K. Takeda,et al.  Low-power embedded ReRAM technology for IoT applications , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[39]  Taejoong Song,et al.  17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[40]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[41]  Eby G. Friedman,et al.  On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits , 2005, Proceedings 2005 IEEE International SOC Conference.

[42]  Fabrizio Lombardi,et al.  A hybrid non-volatile SRAM cell with concurrent SEU detection and correction , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[43]  S. Koveshnikov,et al.  High endurance performance of 1T1R HfOx based RRAM at low (<20μA) operative current and elevated (150°C) temperature , 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.

[44]  Bin Gao,et al.  The Statistical Evaluation of Correlations between LRS and HRS Relaxations in RRAM Array , 2016, 2016 IEEE 8th International Memory Workshop (IMW).

[45]  Gennadi Bersuker,et al.  Advances in RRAM Technology: Identifying and Mitigating Roadblocks , 2016 .

[46]  Qing Dong,et al.  Novel RRAM programming technology for instant-on and high-security FPGAs , 2011, 2011 9th IEEE International Conference on ASIC.

[47]  Gayoung Lee,et al.  Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance , 2016, 2016 IEEE 8th International Memory Workshop (IMW).