Low power TG full adder design using CMOS nano technology

Full adders is the basic building block of ALU and ALU is a basic functioning unit of the microprocessors and DSP. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption. In this paper transmission gates have been used to develop the proposed full adder using 6 transistors XOR gates. The carry logic has been efficiently implemented using 2×1 MUX to reduce transistor count. The reduction in Transistor count results in improved area and power consumption. The proposed full adder has been designed using 27 and 18 transistors using 90 nm technologies. The developed adder with 18 transistors has shown an improvement of 6.624% in power and 31.765% in area so as to implement adder efficiently in digital signal processors.

[1]  V.G. Oklobdzija,et al.  General method in synthesis of pass-transistor circuits , 2000, 2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400).

[2]  . T.Vigneswaran,et al.  A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem , 2008 .

[3]  Vojin G. Oklobdzija,et al.  General method in synthesis of pass-transistor circuits , 2000 .

[4]  M.A. Bayoumi,et al.  A structured approach for designing low power adders , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[5]  Yu-Cherng Hung,et al.  A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[6]  M. A. Bayoumi,et al.  A framework for fair performance evaluation of 1-bit full adder cells , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[7]  Kuo-Hsing Cheng,et al.  The novel efficient design of XOR/XNOR function for adder applications , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[8]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[9]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[10]  S. Panda,et al.  Transistor count optimization of conventional CMOS full adder & optimization of power and delay of new implementation of 18 transistor full adder by dual threshold node design with submicron channel length , 2009, 2009 4th International Conference on Computers and Devices for Communication (CODEC).