The analytic model for noise of direct digital frequency synthesizer
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[1] Franco Maloberti,et al. A direct-digital synthesizer with improved spectral performance , 1991, IEEE Trans. Commun..
[2] J. Jacob Wikner,et al. Modeling of CMOS digital-to-analog converters for telecommunication , 1999 .
[3] H. Samueli,et al. A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .
[4] Richard K. Karlquist. A narrow band high-resolution synthesizer using a direct digital synthesizer followed by repeated dividing and mixing , 1995, Proceedings of the 1995 IEEE International Frequency Control Symposium (49th Annual Symposium).
[5] Jouko Vankka,et al. Spur reduction techniques in sine output direct digital synthesis , 1996, Proceedings of 1996 IEEE International Frequency Control Symposium.
[6] Lawrence J. Kushner,et al. A spurious reduction technique for high-speed direct digital synthesizers , 1996, Proceedings of 1996 IEEE International Frequency Control Symposium.
[7] A. Y. Kwentus,et al. A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range , 1999, IEEE J. Solid State Circuits.
[8] H. Samueli,et al. An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation , 1987, 41st Annual Symposium on Frequency Control.
[9] Tsuneo Tsukahara,et al. A 2V , 2-GHz Low-Power Direct Digital Frequency Synthesizer ChipSet for Wireless Communication , 1998 .
[10] V. K. Kroupa. Discrete spurious signals and background noise in direct frequency synthesizers , 1993, 1993 IEEE International Frequency Control Symposium.
[11] Tsuneo Tsukahara,et al. A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication , 1998 .