Design and implementation of programmable read only memory using reversible decoder on FPGA

Reversible logic is the emerging field for research in present era. The aim of this paper is to design and synthesize a Programmable Read Only Memory (PROM) using a reversible decoder which is designed using reversible logic with minimum quantum cost. The PROM is a Programmable Logic device which consists of fixed AND Gates and programmable OR gates array. Fixed AND gates can be termed as a decoder. PROM finds its applications in cell phones, RFID tags, video game consoles, medical devices, computers and other electronic devices. An n input and k output Boolean function f (a1, a2, a3, ….an) (referred as (n, k)) is said to be logically reversible if and only if, the number of inputs are equal to the number of outputs i.e., ‘n’ equals ‘k’ and the input pattern uniquely maps the output pattern. The reversible logic must run both forward and backward as well such that the inputs can also be retrieved from outputs. There are many reversible logic gates in literature like NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate and many more. Fan-out and Feed-back are not allowed in Logical Reversibility. To overcome the Fan out limitation, the signals from required output lines are duplicated to desired lines using additional reversible combinational circuits. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc., Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, the Programmable Read Only Memory (PROM) using reversible decoder which has less heat dissipation and low power consumption is proposed. The designed circuit is analyzed in terms of quantum cost, garbage outputs and number of gates. The Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN — 3E.

[1]  Jadav Chandra Das,et al.  A novel low power nanoscale reversible decoder using quantum-dot cellular automata for nanocommunication , 2016, 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS).

[2]  A. V. N. Tilak,et al.  Reversible Arithmetic Logic Unit , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[3]  Gopi Chand Naguboina,et al.  Design and synthesis of combinational circuits using reversible decoder in Xilinx , 2017, 2017 International Conference on Computer, Communication and Signal Processing (ICCCSP).

[4]  John P. Hayes,et al.  Synthesis of reversible logic circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  R. Feynman.  Quantum mechanical computers , 1986 .

[6]  K. B. Raja,et al.  Low Power Reversible Parallel Binary Adder/Subtractor , 2010, VLSIC 2010.

[7]  Charles H. Bennett.  Notes on the history of reversible computation , 2000, IBM J. Res. Dev..

[8]  Rolf Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[9]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[10]  Pérès,et al.  Reversible logic and quantum computers. , 1985, Physical review. A, General physics.

[11]  V. Ranganathan,et al.  Design of counters using reversible logic , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[12]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[13]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[14]  Sandeep Saini,et al.  A novel design of reversible 2:4 decoder , 2015, 2015 International Conference on Signal Processing and Communication (ICSC).

[15]  Sandeep Saini,et al.  A novel design of compact reversible SG gate and its applications , 2014, 2014 14th International Symposium on Communications and Information Technologies (ISCIT).

[16]  N. Ranganathan,et al.  Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs , 2010, 2010 23rd International Conference on VLSI Design.