Improvement of Post-Fault Performance of a Cascaded H-bridge Multilevel Inverter

This paper is focused on improving the post-fault performance of cascaded H-bridge multilevel inverters by decreasing the common-mode voltage. First, an algorithm is proposed to determine the optimal post-fault state among all possible states, which have the same maximum available voltage. Furthermore, a modified technique is proposed to calculate the references of inverter phase voltages under faulty conditions. This technique leads to a decrease in the common-mode voltage when the required output voltage is less than its maximum value. These solutions are mutually employed in the post-fault control system. Simulation and experimental results confirm the effectiveness of the proposed solutions in comparison with the existing methods in different cases.