Table of Contents Design, Automation and Test in Europe Conference and Exhibition DATE 2004 Designers' Forum

[1]  Donatella Sciuto,et al.  Analysis and modeling of energy reducing source code transformations , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  Sergio Bampi,et al.  Design of very deep pipelined multipliers for FPGAs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Norbert Wehn,et al.  Channel decoder architecture for 3G mobile wireless terminals , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  Yuan Xie,et al.  LZW-based code compression for VLIW embedded systems , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  Danilo Rimondi,et al.  Building the hierarchy from a flat netlist for a fast and accurate post-layout simulation with parasitic components , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Wolfgang Rosenstiel,et al.  Verification of a microcontroller IP core for system-on-a-chip designs using low-cost prototyping environments , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Luca Benini,et al.  A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[8]  Vittorio Zaccaria,et al.  System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip , 2004, Ultra Low-Power Electronics and Design.

[9]  Altamiro Amadeu Susin,et al.  RASoC: a router soft-core for networks-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[10]  Kuoshu Chiu,et al.  Test infrastructure design for the Nexperia/spl trade/ home platform PNX8550 system chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[11]  Guruprasad Rao,et al.  Qualification and integration of complex I/O in SoC design flows , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[12]  Wolfgang Nebel,et al.  Evaluation of a Refinement-Driven SystemC"-Based Design Flow , 2004, DATE '04.

[13]  Miltos D. Grammatikakis,et al.  OCCN: a network-on-chip modeling and simulation framework , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[14]  Sanjay Dandia.  Package design for high performance ICs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Magdy Saeb,et al.  Design and implementation of a secret key steganographic micro-architecture employing FPGA , 2004 .

[16]  Damien Lyonnard,et al.  Application of a multi-processor SoC platform to high-speed packet forwarding , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[17]  Jean Paul Calvez,et al.  A generic RTOS model for real-time systems simulation with systemC , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[18]  A. Rodriguez-Vazquez,et al.  MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time /spl Sigma//spl Delta/ modulators , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[19]  Shuvra S. Bhattacharyya,et al.  Java-through-C compilation: an enabling technology for Java in embedded systems , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.