A 3GHz subthreshold CMOS low noise amplifier

This paper presents an integrated 3GHz ultra low power CMOS low noise amplifier (LNA) based on a cascode topology where both MOS transistors are biased in subthreshold region. At 160muW DC power consumption and power supply of 0.6V, this LNA has a measured power gain of 4.5dB and noise figure of 6.3dB. At 400muW power consumption, the LNA delivers a power gain of 9.1dB and a noise figure of 4.7dB. The measured IIP3 under 400uAV power dissipation is -11dBm while the input and output matching is better than -13dB. By using a figure of merit that contains the effect of amplifier noise figure, gain, linearity, DC power consumption and operating frequency, we have shown that this amplifier is superior to conventional CMOS LNA designs reported in the literature

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