Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs

Two digital background-calibration techniques are proposed to correct for linearity errors due to capacitor mismatches and opamp nonidealities in the pipelined stages of a pipelined analog-to-digital converters (ADC): 1) capacitor-mismatch calibration: the feedback capacitor is randomly swapped with the sampling capacitor(s) in the multiplying digital-to-analog converter (MDAC) of each pipeline stage, during the normal ADC operation. The capacitor-mismatch errors in all stages are then concurrently calibrated in the digital domain. The proposed technique is applicable to both 1.5- and multi-bit MDACs. In a 13-bit pipelined ADC with 0.25% (1sigma) capacitor-mismatch errors, it improves the SNDR from 10 to 12.5 bits and the SFDR from 65 to 95 dB. 2) interstage-gain calibration: Gain errors due to opamp nonidealities in the MDAC of each pipeline stage are modeled using a 4th-order Taylor series expansion of the opamp output and are digitally calibrated. Compared to previously-reported methods for zero- and 2nd-order gain-calibration, the proposed technique for 4th-order gain-calibration reduces the opamp dc gains required to achieve a 13-bit SNDR in a 14-bit pipelined ADC by 22 dB and 9 dB, respectively. Behavioral simulation results are presented

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