Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm2 radix-4based 8× parallel turbo-decoder ASIC in 0.13 μm CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.

[1]  Gerhard Fettweis,et al.  Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck , 1989, IEEE Trans. Commun..

[2]  In-Cheol Park,et al.  A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[3]  Andries P. Hekstra,et al.  An alternative to metric rescaling in Viterbi decoders , 1989, IEEE Trans. Commun..

[4]  Cheng-Chi Wong,et al.  Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture , 2010, IEEE Journal of Solid-State Circuits.

[5]  János Komlós,et al.  An 0(n log n) sorting network , 1983, STOC.

[6]  E. Szemerédi,et al.  O(n LOG n) SORTING NETWORK. , 1983 .

[7]  A. Burg,et al.  Design and Optimization of an HSDPA Turbo Decoder ASIC , 2009, IEEE Journal of Solid-State Circuits.

[8]  Ran Ginosar,et al.  Parallel VLSI architecture for MAP turbo decoder , 2002, The 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications.

[9]  Lajos Hanzo,et al.  Comparative study of turbo decoding techniques: an overview , 2000, IEEE Trans. Veh. Technol..

[10]  Kenneth E. Batcher,et al.  Sorting networks and their applications , 1968, AFIPS Spring Joint Computing Conference.

[11]  Paul H. Siegel,et al.  VLSI architectures for metric normalization in the Viterbi algorithm , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.

[12]  John B. Anderson,et al.  Concatenated Decoding with a Reduced-Search BCJR Algorithm , 1998, IEEE J. Sel. Areas Commun..

[13]  Marten van Dijk,et al.  Correcting systematic mismatches in computed log-likelihood ratios , 2003, Eur. Trans. Telecommun..

[14]  Brian K. Classon,et al.  ARP and QPP Interleavers for LTE Turbo Coding , 2008, 2008 IEEE Wireless Communications and Networking Conference.

[15]  Qiuting Huang,et al.  A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[16]  Norbert Wehn,et al.  A 150Mbit/s 3GPP LTE Turbo code decoder , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[17]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[18]  Oscar Y. Takeshita,et al.  On maximum contention-free interleavers and permutation polynomials over integer rings , 2005, IEEE Transactions on Information Theory.

[19]  Jon Hamkins,et al.  Coded Modulation for the Deep-Space Optical Channel: Serially Concatenated Pulse-Position Modulation , 2005 .

[20]  Van Nostrand,et al.  Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm , 1967 .

[21]  Alain Glavieux,et al.  Reflections on the Prize Paper : "Near optimum error-correcting coding and decoding: turbo codes" , 1998 .

[22]  Jing Sun,et al.  Interleavers for turbo codes using permutation polynomials over integer rings , 2005, IEEE Transactions on Information Theory.

[23]  Christian Benkeser.  Power efficiency and the mapping of communication algorithms into VLSI , 2010 .

[24]  Cheng-Chi Wong,et al.  A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system , 2009, 2009 Symposium on VLSI Circuits.

[25]  J. Vogt,et al.  Improving the max-log-MAP turbo decoder , 2000 .

[26]  M. Bickerstaff,et al.  A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..