Embedded Memories: Introduction

This chapter provides a short introduction to the field of embedded memories for VLSI systems-on-chip (SoCs). A review of data published in the last few decades show a steadily increasing need for embedded memories in VLSI SoCs, and predictions from the International Technology Roadmap for Semiconductors (ITRS) indicate that this trend will continue. The chapter reviews various recent VLSI SoCs to exemplify the dominant area and power shares, which embedded memories consume. Specific memory requirements of different classes of VLSI SoCs, from ultra-low power to power-aware high-performance systems, are presented next. Finally, a short review of the state-of-the-art embedded memory technologies, including static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM), is provided, before closing the chapter with a book outline.

[1]  Fan Zhang,et al.  A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Paolo A. Aseron,et al.  2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  A. Burg,et al.  Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes , 2008, 2008 42nd Asilomar Conference on Signals, Systems and Computers.

[4]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[5]  M. Sachdev,et al.  Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC , 2009, IEEE Journal of Solid-State Circuits.

[6]  Hubert Kaeslin,et al.  Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication , 2008 .

[7]  Anantha Chandrakasan,et al.  Challenges and Directions for Low-Voltage SRAM , 2011, IEEE Design & Test of Computers.

[8]  Scott A. Mahlke,et al.  Diet SODA: A power-efficient processor for digital cameras , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[9]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[10]  Anantha Chandrakasan,et al.  An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor , 2012, 2012 IEEE International Solid-State Circuits Conference.

[11]  Adam Teman,et al.  A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[13]  A. Burg,et al.  Review and classification of gain cell eDRAM implementations , 2012, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel.

[14]  Shin Min Kang,et al.  CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .

[15]  David Atienza,et al.  Design of energy efficient and dependable health monitoring systems under unreliable nanometer technologies , 2012, BODYNETS.

[16]  David Atienza,et al.  TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[17]  Luca Benini,et al.  Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement , 2016, TODE.

[18]  Mark Bohr,et al.  The new era of scaling in an SoC world , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[19]  Andreas Peter Burg,et al.  Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[20]  Christoph Roth,et al.  On the exploitation of the inherent error resilience of wireless systems under unreliable silicon , 2012, DAC Design Automation Conference 2012.

[21]  Partha Pratim Pande,et al.  Design Technologies for Green and Sustainable Computing Systems , 2013 .

[22]  Paolo A. Aseron,et al.  A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance , 2011, IEEE Journal of Solid-State Circuits.

[23]  Jan M. Rabaey,et al.  SRAM supply voltage scaling: A reliability perspective , 2009, 2009 10th International Symposium on Quality Electronic Design.