A massively parallel SIMD algorithm for combinatorial optimization

Many significant engineering and scientific problems involve optimization of some criteria over a combinatorial configuration space. The two methods most often used to solve these problems effectively-simulated annealing (SA) and genetic algorithms (GA)-do not easily lend themselves to massive parallel implementations. This paper introduces a new hybrid algorithm that inherits those aspects of GA that lend themselves to parallelization, and avoids serial bottlenecks of GA approaches by incorporating elements of SA to provide a completely parallel, easily scalable hybrid GA/SA method. This new method, called genetic simulated annealing, does not require parallelization of any problem specific portions of a serial implementation-existing serial implementations can be incorporated as-is. Results of a study on two difficult combinatorial optimization problems, a 100 city traveling salesperson problem and a 24 word, 12 bit error correcting code design problem, performed on a 16 K PE MasPar MP-1, indicate significant advantages of the method. One of the key results is that the performance of the algorithm scales up almost linearly with the increase of processing elements. Additionally, the algorithm does not require careful choice of control parameters, a significant advantage over SA and GA.

[1]  Gary B. Lamont,et al.  Comparison of Parallel Messy Genetic Algorithm Data Distribution Strategies , 1993, ICGA.

[2]  Hao Chen,et al.  Parallel Simulated Annealing and Genetic Algorithms: a Space of Hybrid Methods , 1994, PPSN.

[3]  Kejitan Domas Discovery of Maximal Distance Codes Using Genetic Algorithms , 1990 .

[4]  Rob A. Rutenbar,et al.  Placement by Simulated Annealing on a Multiprocessor , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Runhe Huang,et al.  Implementing the Genetic Algorithm on Transputer Based Parallel Processing Systems , 1990, PPSN.

[6]  Howard Jay Siegel,et al.  Mapping computer-vision-related tasks onto reconfigurable parallel-processing systems , 1992, Computer.

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Tom Blank,et al.  The MasPar MP-1 architecture , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[9]  Daniel R. Greening,et al.  Parallel simulated annealing techniques , 1990 .

[10]  Lane A. Hemaspaandra,et al.  Using simulated annealing to design good codes , 1987, IEEE Trans. Inf. Theory.