Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers
暂无分享,去创建一个
[1] T. Nakagawa,et al. A novel phase noise reduction technique for MMIC frequency synthesizers that uses newly developed pulse generator LSI , 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).
[2] F. Jager,et al. Tamed Frequency Modulation, A Novel Method to Achieve Spectrum Economy in Digital Transmission , 1978, IEEE Trans. Commun..
[3] Yo Yamaguchi,et al. 1.9 GHz-band low voltage and low power consumption RF IC chip-set for personal communications , 1994, Proceedings of IEEE Vehicular Technology Conference (VTC).
[4] Shuzo Kato,et al. Low power consumption and fast settling frequency synthesizer for TDMA-TDD systems , 1993, IEEE 43rd Vehicular Technology Conference.
[5] J. H. Havens,et al. A 2.7 V to 4.5 V single-chip GSM transceiver RF integrated circuit , 1995 .
[6] D. Stolfa,et al. A Single-chip, 1.2 Ghz, PLL frequency synthesizer Using Reduced Capacitance, dual gate, BiCMOS technology , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.
[7] T. Kamoto,et al. High-speed multi-modulus prescaler IC , 1995, Proceedings of ICUPC '95 - 4th IEEE International Conference on Universal Personal Communications.
[8] Robert G. Meyer,et al. Future directions in silicon ICs for RF personal communications , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[9] T. Kwasniewski,et al. CMOS high-speed dual-modulus frequency divider for RF frequency synthesis , 1995 .
[10] Byungsoo Chang,et al. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops , 1996 .
[11] J. H. Havens,et al. A 900 MHz transceiver chip set for dual-mode cellular radio mobile terminals , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[12] T.A. Kwasniewski,et al. A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
[13] Behzad Razavi,et al. A 2-GHz, 6-mW BiCMOS frequency synthesizer , 1995 .
[14] S. Pasupathy,et al. Minimum shift keying: A spectrally efficient modulation , 1979, IEEE Communications Magazine.
[15] Shinsaku Mori,et al. Fast acquisition frequency synthesizer with n-stage novel type cycle swallowers , 1992, [Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications.
[16] Alfonso Fernández-Durán,et al. Single loop synthesizer and modulator based on a quadratic correlation architecture , 1994, Proceedings of IEEE Vehicular Technology Conference (VTC).
[17] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[18] Asad A. Abidi. Direct-conversion radio transceivers for digital communications , 1995 .
[19] K. Hirade,et al. GMSK Modulation for Digital Mobile Radio Telephony , 1981, IEEE Trans. Commun..
[20] Wing Shing Djen,et al. Implementation of a 900 MHz transmitter system using highly integrated ASIC , 1994, Proceedings of IEEE Vehicular Technology Conference (VTC).
[21] Shyh-Jye Jou,et al. A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design , 1995 .
[22] D. Leeson. A simple model of feedback oscillator noise spectrum , 1966 .
[23] Michiel Steyaert,et al. A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μM CMOS , 1996, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.
[24] P. D. Roberts,et al. Linear Control System Analysis and Design , 1982 .
[25] W. Siebert. Circuits, Signals and Systems , 1985 .
[26] J. Sevenhans,et al. An integrated Si bipolar RF transceiver for a zero IF 900 MHz GSM digital mobile radio frontend of a hand portable phone , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.
[27] Ulrich L. Rohde. Digital PLL frequency synthesizers , 1982 .
[28] R. Brodersen,et al. A low-power CMOS chipset for spread spectrum communications , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[29] H. Sato,et al. A 1.9 GHz single-chip IF transceiver for digital cordless phones , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[30] Floyd M. Gardner,et al. Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.
[31] Stefan Beyer,et al. A 3.0 V 2 GHz transmitter IC for digital radio communication with integrated VCOs , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[32] G. Sauvage. Phase Noise in Oscillators: A Mathematical Analysis of Leeson's Model , 1977, IEEE Transactions on Instrumentation and Measurement.
[33] M. Ishikawa,et al. A miniaturized low-power synthesizer module with automatic frequency stabilization (for portable telephone applications) , 1992, [1992 Proceedings] Vehicular Technology Society 42nd VTS Conference - Frontiers of Technology.
[34] Gabor C. Temes,et al. Oversampling Delta Sigma Data Converters , 1991 .
[35] T. Riley,et al. Delta-sigma modulation in fractional-N frequency synthesis , 1993 .
[36] M.A. Copeland. VLSI for analog/digital communications , 1991, IEEE Communications Magazine.
[37] M. A. Copeland,et al. A simplified continuous phase modulator technique , 1994 .
[38] R. Ziemer,et al. Minimum-shift keyed modem implementations for high data rates , 1983, IEEE Communications Magazine.
[39] H. Ichino,et al. 18-GHz 1/8 dynamic frequency divider using Si bipolar technologies , 1989 .
[40] John G. Proakis,et al. Digital Communications , 1983 .
[41] M. Nakagawa,et al. A new PLL frequency synthesizer with high switching speed , 1992 .
[42] Didier Rene Haspeslagh,et al. An analog radio front-end chip set for a 1.9 GHz mobile radio telephone application , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[43] B.D. Unter. Frequency synthesizers: Theory and design , 1979, Proceedings of the IEEE.
[44] N. Tracht,et al. A sub-1 mA 1.5 GHz silicon bipolar dual modulus prescaler , 1993, 1993 Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.
[45] D. A. Williams. A frequency hopping microwave radio system for local area network communications , 1993, 1993 IEEE MTT-S International Microwave Symposium Digest.
[46] V. Thomas,et al. A 2.7 V 2.5 GHz bipolar chipset for digital wireless communication , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[47] K. McNab,et al. A Short Survey of Frequency Synthesizer Techniques , 1986, 40th Annual Symposium on Frequency Control.
[48] R. M. Herman,et al. An integrated GPS receiver with synthesizer and downconversion functions , 1991, 1991 IEEE MTT-S International Microwave Symposium Digest.
[49] B. Miller,et al. A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.
[50] Asad A. Abidi,et al. An all-CMOS architecture for a low-power frequency-hopped 900 MHz spread spectrum transceiver , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
[51] R. G. Irvine,et al. An RF front-end for digital mobile radio , 1990, Proceedings on Bipolar Circuits and Technology Meeting.
[52] S. Mori,et al. Fast acquisition frequency synthesizer with the multiple phase detectors , 1991, [1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings.
[53] George S. Moschytz. MOS switched-capacitor filters : analysis and design , 1984 .
[54] Behzad Razavi,et al. Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS , 1995, IEEE J. Solid State Circuits.
[55] H. Samueli,et al. A 200 MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design , 1993 .
[56] Dov Wulich. Fast frequency synthesis by PLL using a continuous phase divider , 1988 .