Efficient C level hardware design for floating point biomedical DSP applications

Recent advances in embedded system design has increased their interference in different application domains, where software only solutions have prevailed. This new implementation platform require however quality of results in terms of speed, power and computational complexity, along with strict time-to-market schedules. Performance is sought by utilizing modern Field Programmable Gate Array (FPGA) devices, offering hundreds of GFLOPs with maximum power efficiency. Productivity is enforced with High-Level Synthesis (HLS) or Electronic System Level (ESL) or C-based hardware design methodologies, that offer an efficient abstraction level to boost-up early prototyping. However, just like the migration from schematics to Hardware Description Languages (HDLs) required specific coding styles for efficient hardware design, C-based hardware design also requires efficient coding guidelines to be followed. This paper presents a set of such coding guidelines, and evaluates their efficiency for FPGA based scientific, floating point arithmetic calculations. As found through extensive experimentation, the performance and area optimizations offered by efficient coding can improve the ones offered by HLS only, even more than 90%. So, while not every C program can be turned into hardware with the press of a button, efficient coded C programs can offer a profitable productivity boost.