Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM

Spin-transfer torque random access memory (STT-RAM) has emerged as a promising nonvolatile memory technology for its fast speed, small footprint and zero standby power. However, the unique and unusual high asymmetric error rates at different memory bit operations, which are proved to be far beyond the efficiency of common error correction codes (ECCs), greatly hinder its applications. In this work, we investigate the potentials of the powerful low-density parity-check (LDPC) code to address the aggravated reliability issue in STT-RAM. We first develop a holistic STT-RAM channel model to quantitatively measure the asymmetric effects during the write and read process for single-level-cell (SLC) and multi-level-cell (MLC) design. We then propose an asymmetric LDPC (A-LDPC) decoding to particularly enhance the asymmetric error correcting capability. An STT-RAM dedicated hardware-favorable soft information, namely asymmetric Log-Likelihood Ratio (A-LLR), is also derived from the proposed channel model. Experimental results show that our A-LDPC can outperform at least two/four orders of magnitude over existing ECCs for combating the asymmetric bit errors in SLC/MLC STT-RAM.