Genetic algorithm-based FSM synthesis with area-power trade-offs

Traditionally, state-encoding strategies targeting minimization of area, dynamic power or a combination of them have been utilized in finite state machine (FSM) synthesis. With drastic scaling down of devices at recent technology level, leakage power has also become an important design parameter to be considered during synthesis. A genetic algorithm-based state encoding, targeting area and power minimized FSM, has been proposed in this paper. A unified technique to reduce both static power (leakage) and dynamic power along with area trade-off has been carried out for FSM synthesis, targeting static CMOS NAND-NAND PLA, dynamic CMOS NOR-NOR PLA and pseudo-NMOS NOR-NOR PLA implementations. Suitable weights for area, leakage power and dynamic power to minimize power density have also been explored. Simulation with MCNC benchmarks shows an average improvement of 31%, 26% and 29% in leakage power consumption, dynamic power consumption and area requirement respectively, over NOVA-based state assignment technique in case of dynamic CMOS PLA implementation. Improvements of 30% in leakage power and 15% in area have been obtained for pseudo-NMOS PLA implementation. For the static CMOS case, the improvements are about 29% in leakage power consumption, 14% in dynamic power consumption and 18% in area requirement.

[1]  Feng Gao,et al.  ILP-based optimization of sequential circuits for low power , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[2]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[3]  José C. Monteiro,et al.  Finite state machine decomposition for low power , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[4]  Reiner Kolla,et al.  Spanning tree based state encoding for low power dissipation , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[5]  C. Silvano,et al.  Low-power state assignment techniques for finite state machines , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[6]  Massoud Pedram,et al.  Low power synthesis of finite state machines with mixed D and T flip-flops , 2003, ASP-DAC '03.

[7]  Klaus Feske,et al.  State assignment for FSM low power design , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[8]  Luca Benini,et al.  Automatic synthesis of low-power gated-clock finite-state machines , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Luca Benini,et al.  Transformation and synthesis of FSMs for low-power gated-clock implementation , 1995, ISLPED '95.

[10]  B.F. Tawadros,et al.  Characterizing standby leakage in high-performance flip-flops considering both subthreshold and gate leakage , 2004, International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04..

[11]  Luca Benini,et al.  State assignment for low power dissipation , 1995 .

[12]  J. Huertas,et al.  0 FSMTEST : SYNTHESIS FOR TESTABILITY AND TEST GENERATION OF PLA-BASED FSMS , 1992 .

[13]  Gang Qu,et al.  FSM re-engineering and its application in low power state encoding , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[14]  A. Despain,et al.  Low Power State Assignment Targeting Two- And Multi-level Logic Implementations , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[15]  Robbert Eggermont,et al.  Profiling-based State Assignment for Low Power Dissipation , 2003 .

[16]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[17]  Youn-Long Lin,et al.  State assignment for power and area minimization , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[18]  Irith Pomeranz,et al.  GALLOP: genetic algorithm based low power FSM synthesis by simultaneous partitioning and state assignment , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[19]  Kaushik Roy,et al.  SYCLOP: synthesis of CMOS logic for low power applications , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[20]  Manoj Sachdev,et al.  Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems) , 2006 .

[21]  Chi-Ying Tsui,et al.  Finite state machine partitioning for low power , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[22]  Tiziano Villa,et al.  An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Xunwei Wu,et al.  Low power sequential circuit design using priority encoding and clock gating , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[24]  TingTing Hwang,et al.  Low power realization of finite state machines—a decomposition approach , 1996, TODE.

[25]  Sungju Park,et al.  A now state assignment technique for testing and low power , 2004, Proceedings. 41st Design Automation Conference, 2004..

[26]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[27]  Manoj Sachdev,et al.  Thermal and Power Management of Integrated Circuits , 2006, Series on Integrated Circuits and Systems.

[28]  Santanu Chattopadhyay,et al.  Low power state assignment and flipflop selection for finite state machine synthesis: a genetic algorithmic approach , 2001 .

[29]  J. Griffiths.  The Theory of Stochastic Processes , 1967 .

[30]  Santanu Chattopadhyay,et al.  Finite state machine state assignment targeting low power consumption , 2004 .

[31]  José C. Monteiro,et al.  FSM decomposition by direct circuit manipulation applied to low power design , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[32]  Akhilesh Tyagi,et al.  Low power FSM design using Huffman-style encoding , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[33]  Santanu Chattopadhyay,et al.  Synthesis of Finite State Machines for Low Power and Testability , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[34]  B.F. Tawadros,et al.  State assignment for low-leakage finite state machines , 2005, The 3rd International IEEE-NEWCAS Conference, 2005..

[35]  Yinshui Xia,et al.  Genetic algorithm based state assignment for power and area optimisation , 2002 .