Use of Non-linear Solver to Check Assertions of Behavioral Descriptions

Verification has become an essential aspect of design flow because of the increasing design complexity. According to the latest report of the International Technology Roadmap for Semiconductor, the challenge will be to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several Design-forVerifiability methodologies (DFV) have been proposed and Assertion-based Verification (ABV) is one of the most promising. In order to automatically verify assertions at the higher abstraction levels, it is necessary to improve the performance and capabilities of current constraint solvers. This paper presents a new technique based on non-linear solvers that automatically checks assertions in behavioral descriptions of hardware systems. The main contribution of this work is the definition of a methodology that allows using continuous non-linear solvers to verify behavioral descriptions. These descriptions are modeled with a set of integer polynomial inequalities. The technique provides better results than integer solvers and it is applied to real designs, such as Viterbi decoders or vocoder digital filters. Keywords—Assertion Checker, Design for Verifiability, Nonlinear solvers.