Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach

Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modifies the faulty behavior of the memory. This paper introduces an analytical (equation-based) method to give a rough analysis of the faulty behavior of cell opens in the memory, that simplifies the understanding and identifies the major factors responsible for the faulty behavior. Having these factors makes it easier to optimize the circuit and allows extrapolation of the behavior of future technologies. The paper also compares the results of the analytical approach with those from the simulation-based analysis and discusses the advantages and disadvantages of both

[1]  NaikSamir,et al.  Failure Analysis of High-Density CMOS SRAMs , 1993 .

[2]  Jörg E. Vollrath.  Cell signal measurement for high-density DRAMs , 1997, Proceedings International Test Conference 1997.

[3]  Ad J. van de Goor,et al.  Approximating infinite dynamic behavior for DRAM cell defects , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[4]  John L. Wyatt,et al.  Mismatch sensitivity of a simultaneously latched CMOS sense amplifier , 1991 .

[5]  Wojciech Maly,et al.  Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing , 1993, IEEE Design & Test of Computers.

[6]  Jörg E. Vollrath.  Tutorial: synchronous dynamic memory test construction-a field approach , 2000, Records of the IEEE International Workshop on Memory Technology, Design and Testing.