A self-cascode pseudo floating gate front-end for resonating sensors

In this work, we have demonstrated an alternative design strategy based on self-cascode transistors to improve the gain and the power consumption of a pseudo floating gate amplifier (PFGA), with the minimum area occupation. This is accomplished by implementing the inverter in the PFGA using self-cascode transistors, which provides all the advantages of a cascode amplifier (higher gain and lower power consumption), with a negligible overhead in terms of area occupation. The performance of a self-cascode pseudo floating gate amplifier (SC-PFGA) are comparable to those ones of a current-starved pseudo floating gate amplifier (CS-PFGA), with the difference that CS-PFGA requires also the circuitry to generate two reference voltages. For this reason the SC-PFGA is more compact and less power consuming than a CS-PFGA. On the other hand, the SC-PFGA doesn't provide the possibility to tune the bandwidth or the gain of the amplifier, which can be negligible in applications in which this feature is not necessary. In this work, we have compared the performance between PFGA and SC-PFGA by designing and simulating these circuits in AMS-350nm CMOS process with a power supply of 5V. This specific implementation can be applied in all those systems in which low leakage currents or voltages higher than 5V are required. In order to prove the effectiveness of this technique, the amplifier has been tested as analog front-end of a generic resonating sensor approximated with a Butterworth Van Dike model. Simulation results show that the self cascode amplifier provides a gain 7 times greater and a power consumption 12 times smaller than the ones provided by the PFGA.