A comparison of 10 GHz frequency dividers in bulk and SOI 0.13 /spl mu/m CMOS technologies
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The goal of this paper is to focus on the advantages of SOI technologies for high speed digital circuits for RF application, through the study of the consumption of 10 GHz frequency dividers. Dynamic and static structures are implemented in bulk and SOI CMOS 0.13 /spl mu/m technologies, and the measured consumptions are compared. As the capacitance of the drain-source diffusions and interconnections are reduced in SOI because of the BOX, dynamic consumption reductions of 20 % and 25 % are measured between bulk and SOI technologies, respectively for the dynamic and static structure.
[1] Behzad Razavi,et al. Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS , 1995, IEEE J. Solid State Circuits.
[2] K. A. Jenkins,et al. Transient effects in floating body SOI NMOSFETs , 1995, 1995 IEEE International SOI Conference Proceedings.
[3] D. L. Stasiak,et al. A 440-ps 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology , 2001 .