Bit error rate analysis in Charge Trapping memories for SSD applications

Different program algorithms are experimentally characterized on CT-NAND Flash Arrays at 4X technology node. The advantages in terms of endurance, retention and read disturb reduction obtained with the proposed algorithms are shown. The positive effects of these algorithms can be increased using an error-reduction procedure called Read Retry, making feasible the usage of CT-NAND memories in MLC-SSD applications.

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