Design for variability in CMOS logic circuits: Uncommitted motif arrays (UMAs)
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[1] A. Asenov,et al. Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.
[2] S. Griffis. EDITOR , 1997, Journal of Navigation.
[3] S. L. Hurst,et al. A Highly Routable ULM Gate Array and Its Automated Customizaton , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Linard Karklin,et al. Layout techniques and rules to reduce process-related variability , 2007 .
[5] Frank R. Ramsay. Automation of Design for Uncommitted Logic Array , 1980, 17th Design Automation Conference.
[6] Shekhar Y. Borkar,et al. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.
[7] Asen Asenov,et al. Investigation into effects of device variability on CMOS layout motifs , 2008 .
[8] Víctor H. Champac,et al. A design methodology for logic paths tolerant to local intra-die variations , 2008, 2008 IEEE International Symposium on Circuits and Systems.