SRAM Cells for Embedded Systems

Static Random Access Memories (SRAMs) continue to be critical components across a wide range of microelectronics applications from consumer wireless to high performance server processors, multimedia and System on Chip (SoC) applications. It is also projected that the percentage of embedded SRAM in SoC products will increase further from the current 84% to as high as 94% by the year 2014 according to the International Technology Roadmap for Semiconductors (ITRS). This trend has mainly grown due to ever increased demand of performance and higher memory bandwidth requirement to minimize the latency, therefore, larger L1, L2 and even L3 caches are being integrated on-die. Hence, it may not be an exaggeration to say that the SRAM is a good technology representative and a powerful workhorse for the realization of modern SoC applications and high performance processors.

[1]  S. Natarajan,et al.  SE5 - SRAM design in the nanoscale era , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[3]  P. Bai,et al.  A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[4]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[5]  S. Kosonocky,et al.  Fluctuation limits & scaling opportunities for CMOS SRAM cells , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[6]  Kaushik Roy,et al.  A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  T. Fukai,et al.  Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies , 2007, 2007 IEEE International Electron Devices Meeting.

[8]  N. Kasai,et al.  A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[9]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[10]  M. Yamaoka,et al.  SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors , 2006, IEEE Journal of Solid-State Circuits.

[11]  N. Vallepalli,et al.  A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[12]  Shin Min Kang,et al.  CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .

[13]  K. Roy,et al.  Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[14]  Marios C. Papaefthymiou,et al.  Constant-load energy recovery memory for efficient high-speed operation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[15]  R. Engelbrecht,et al.  DIGEST of TECHNICAL PAPERS , 1959 .

[16]  Borivoje Nikolic,et al.  Design Trade-offs of a 6 T FinFET SRAM Cell in the Presence of Variations , 2007 .

[17]  Farhana Sheikh,et al.  The Impact of Device-Width Quantization on Digital Circuit Design Using FinFET Structures , 2022 .

[18]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[19]  A. Sedra.  Microelectronic circuits , 1982 .

[20]  A. Ogura,et al.  Sub-10-nm planar-bulk-CMOS devices using lateral junction control , 2003, IEEE International Electron Devices Meeting 2003.

[21]  Gary K. Yeap,et al.  Practical Low Power Digital VLSI Design , 1997 .

[22]  N. Vallepalli,et al.  SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction , 2005, IEEE Journal of Solid-State Circuits.

[23]  Jan M. Rabaey,et al.  SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[24]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[25]  Naveen Verma,et al.  Design considerations for ultra-low energy wireless microsensor nodes , 2005, IEEE Transactions on Computers.

[26]  Zheng Guo,et al.  FinFET-based SRAM design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[27]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[28]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[29]  Anantha P. Chandrakasan,et al.  Subthreshold Circuit Techniques , 2004 .

[30]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[31]  Masahiro Nomura,et al.  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[32]  Donggun Park,et al.  Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs) , 2006, IEEE Transactions on Electron Devices.

[33]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[34]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[35]  Joachim Keinert,et al.  Scaling beyond the 65 nm node with FinFET-DGCMOS , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[36]  Kaushik Roy,et al.  Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits , 2005 .

[37]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[38]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.