New lower bound techniques for VLSI

In this paper, we use crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, we describe1)anN-node planar graph which has layout area θ(NlogN) and maximum edge length θ(N1/2/log1/2N),2)anN-node graph with anO(x1/2)-separator which has layout area θ(Nlog2N) and maximum edge length θ(N1/2logN/loglogN), and3)anN-node graph with anO(x1−1/r)-separator which has maximum edge length θ(N1−1/r) for anyr ≥ 3.

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