Design of a MCML Gate Library Applying Multiobjective Optimization

In this paper, the problem of sizing MOS current mode logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 mum technology are presented.

[1]  L. A. MacEachern.  Constrained circuit optimization via library table genetic algorithms , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Masayuki Mizuno,et al.  A GHz MOS adaptive pipeline technique using MOS current-mode logic , 1996, IEEE J. Solid State Circuits.

[3]  Georges G. E. Gielen,et al.  Performance space modeling for hierarchical synthesis of analog integrated circuits , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[4]  José Pablo Alvarado Moya,et al.  Segmentation of color images for interactive 3D object retrieval , 2004 .

[5]  Mohamed I. Elmasry,et al.  MOS current mode circuits: analysis, design, and variability , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  A.H. Ismail,et al.  On the design of low power MCML based ring oscillators , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

[7]  Martin J. Oates,et al.  The Pareto Envelope-Based Selection Algorithm for Multi-objective Optimisation , 2000, PPSN.

[8]  Dong Sam Ha,et al.  Gigahertz-range MCML multiplier architectures , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  Jan M. Rabaey,et al.  MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[10]  Mohamed I. Elmasry,et al.  MOS current mode logic: design, optimization, and variability , 2004, IEEE International SOC Conference, 2004. Proceedings..

[11]  Georges G. E. Gielen,et al.  HOLMES: capturing the yield-optimized design space boundaries of analog and RF integrated circuits , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[12]  Ulf Schlichtmann,et al.  Deterministic approaches to analog performance space exploration (PSE) , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[13]  Paul Husted,et al.  An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic , 2000 .

[14]  Georges G. E. Gielen,et al.  WATSON: design space boundary exploration and model generation for analog and RFIC design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..