Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics
暂无分享,去创建一个
Meng-Fan Chang | Jia-Min Shieh | Albert Lee | Pei-Ling Tseng | Chien-Fu Chen | Chia-Chen Kuo | Ping-Cheng Chen | Tzu-Kun Ku | Chien-Chen Lin | Mon-Shu Ho | Ming-Pin Chen | Kai-Shin Li
[1] K. S. Choi,et al. Highly productive PCRAM technology platform and full chip operation: Based on 4F2 (84nm pitch) cell scheme for 1 Gb and beyond , 2011, 2011 International Electron Devices Meeting.
[2] H. C. Jung,et al. NbO2-based low power and cost effective 1S1R switching for high density cross point ReRAM Application , 2014, Symposium on VLSI Technology.
[3] HfO2 Bipolar Resistive Memory Device with Robust Endurance using AlCu as Electrode , 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
[4] A. Sebastian,et al. Drift-resilient cell-state metric for multilevel phase-change memory , 2011, 2011 International Electron Devices Meeting.
[5] Mark A. Taylor,et al. A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[6] S. J. Kim,et al. Low power operating bipolar TMO ReRAM for sub 10 nm era , 2010, 2010 International Electron Devices Meeting.
[7] Shoji Ikeda,et al. A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme , 2010, IEEE Journal of Solid-State Circuits.
[8] Tohru Ozaki,et al. A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes , 2010, IEEE Journal of Solid-State Circuits.
[9] Meng-Fan Chang,et al. An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory , 2011, 2011 IEEE International Solid-State Circuits Conference.
[10] Peilin Song,et al. 1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing , 2013, 2013 Symposium on VLSI Circuits.
[11] Meng-Fan Chang,et al. A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications , 2010, 2010 Symposium on VLSI Circuits.
[12] L. Goux,et al. Stochastic variability of vacancy filament configuration in ultra-thin dielectric RRAM and its impact on OFF-state reliability , 2013, 2013 IEEE International Electron Devices Meeting.
[13] Tohru Ozaki,et al. A 100MHz ladder FeRAM design with capacitance-coupled-bitline (CCB) cell , 2010, 2010 Symposium on VLSI Circuits.
[14] Meng-Fan Chang,et al. A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
[15] M. Tsai,et al. Ultra high density 3D via RRAM in pure 28nm CMOS process , 2013, 2013 IEEE International Electron Devices Meeting.
[16] Meng-Fan Chang,et al. ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.
[17] S.W. Nam,et al. High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications , 2010, 2010 Symposium on VLSI Technology.
[18] Tom Zhong,et al. Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
[19] Jing Li,et al. 1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing , 2014, IEEE Journal of Solid-State Circuits.
[20] Tohru Ozaki,et al. A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell , 2011, IEEE Journal of Solid-State Circuits.
[21] Ogun Turkyilmaz,et al. RRAM-based FPGA for “normally off, instantly on” applications , 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).
[22] Meng-Fan Chang,et al. 19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[23] M. Aoki,et al. A novel MTJ for STT-MRAM with a dummy free layer and dual tunnel junctions , 2012, 2012 International Electron Devices Meeting.
[24] M. Tsai,et al. Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays , 2014, IEEE Journal of the Electron Devices Society.
[25] Doris Schmitt-Landsiedel,et al. Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive , 2012, 2012 IEEE International Solid-State Circuits Conference.
[26] Anantha Chandrakasan,et al. A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[27] Naoki Kasai,et al. Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs , 2009, IEEE J. Solid State Circuits.
[28] Y. Shih,et al. A forming-free WOx resistive memory using a novel self-aligned field enhancement feature with excellent reliability and scalability , 2010, 2010 International Electron Devices Meeting.
[29] David Blaauw,et al. 13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[30] Masahide Matsumoto,et al. A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology , 2014, IEEE Journal of Solid-State Circuits.
[31] Meng-Fan Chang,et al. A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time , 2012, 2012 IEEE International Solid-State Circuits Conference.
[32] T. Yamamoto,et al. Charge-injection phase change memory with high-quality GeTe/Sb2Te3 superlattice featuring 70-μA RESET, 10-ns SET and 100M endurance cycles operations , 2013, 2013 IEEE International Electron Devices Meeting.
[33] T. Endoh,et al. Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine , 2013, 2013 Symposium on VLSI Technology.
[34] Yukio Hayakawa,et al. An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput , 2012, IEEE Journal of Solid-State Circuits.
[35] Hugh P. McAdams,et al. An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at ${\rm VDD}=$ 0 V Achieving Zero Leakage With ${<}$ 400-ns Wakeup Time for ULP Applications , 2014, IEEE Journal of Solid-State Circuits.