In this paper, optimum transistor sizing of clock-gated master slave flip-flops viz. Gated Master Slave Latch (GMSL) and clock-gated Transmission Gate Flip-flop (CG-TGFF) has been implemented for high performance based on Logical Effort (LE) theory. In contrast to the previous work where clock-gating was merely utilized only for reduction of total dynamic power dissipation, we have also optimized the delay caused due to addition of extra transistors for clock-gating circuit. A comparative study of power-delay product (PDP) and power-delay-area product (PDAP) for the aforementioned circuits is performed. Simulation results using 180nm/1.8V TSMC CMOS technology have indicated that GMSL offers upto 45.8% and 49.6% improvement in PDP and PDAP respectively when compared to CG-TGFF at 0% switching activity (all ones). Results have been verified for various switching activities of the data input with respect to clock signal frequency.
[1]
Robert W. Brodersen,et al.
Analysis and design of low-energy flip-flops
,
2001,
ISLPED '01.
[2]
Massimo Alioto,et al.
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies
,
2011,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3]
Hiroshi Kawaguchi,et al.
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
,
1998,
IEEE J. Solid State Circuits.
[4]
Davide De Caro,et al.
New clock-gating techniques for low-power flip-flops
,
2000,
ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).