An Area-Efficient FPGA Implementation of a Disparity Estimation Scheme for Real-Time Compression of IP Images *

The interest for real three dimensional displays has been revived over the past few years, and the high resolution images that capturing and reproducing of 3D imagery demands, must be addressed with an efficient compression scheme. An area-efficient hardware implementation of a real-time disparity estimation scheme targeted to Integral Photography 3D images is presented, exploiting the inherent redundancy of Integral Photography images, coping with the increased bandwidth that this technology requires.

[1]  S. Ramachandran,et al.  FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression , 2001, FPGA '01.

[2]  Stamatis Vassiliadis,et al.  A sum of absolute differences implementation in FPGA hardware , 2002, Proceedings. 28th Euromicro Conference.

[3]  N. P. Sgouros,et al.  Compression of IP images for autostereoscopic 3D imaging applications , 2003, 3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the.

[4]  Hongen Liao,et al.  Intra-operative Real-Time 3-D Information Display System Based on Integral Videography , 2001, MICCAI.

[5]  Stephan Wong,et al.  Alternatives in FPGA-based SAD implementations , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[6]  Ville Kyrki.  Jbig Image Compression Standard , 1999 .

[7]  P. Harman,et al.  Home based 3D entertainment-an overview , 2000, Proceedings 2000 International Conference on Image Processing (Cat. No.00CH37101).

[8]  Janusz Konrad,et al.  Visual communications of tomorrow: natural, efficient, and flexible , 2001, IEEE Commun. Mag..

[9]  M. Halle.  Autostereoscopic displays and computer graphics , 1997, COMG.

[10]  Gert Slavenburg,et al.  An architectural overview of the programmable multimedia processor, TM-1 , 1996, COMPCON '96. Technologies for the Information Superhighway Digest of Papers.