Electrical Design of Digital Multichip Modules

The aims in package electrical design are to maximize the performance of the system, as limited by the interconnect (here “interconnect” refers to interconnections and connections) delay, while minimizing the possibility of false operation in the field, due to electrical noise, and minimizing the cost. To this end, electrical design of digital systems consists of the following: 1 Selecting the appropriate packaging and semiconductor technology mixture, and the appropriate partitioning of functions between chips and packages, so that the system design is likely to meet its cost and performance aims (see Chapter 3) 2 Generating the logical design (gate level design), and determining the logic families to be used 3 Generating the timing design (when signal events will take place) and the noise budget (the required signal quality or signal integrity) 4 Determining the appropriate models and selecting the appropriate simulation tools that allow interconnect signals and timing to be accurately predicted from the physical design 5 Generating the physical design. This includes a placement, which describes where the chips and other components are located, and a layout, which describes where conductors run.

[1]  Arnold Reisman,et al.  Thin-film pulse propagation analysis using frequency techniques , 1991 .

[2]  D. Nguyen,et al.  Performance modeling of a cache system with three interconnect technologies: cyanate ester PCB, chip-on-board and Cu/PI MCM , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[3]  A. H. Engvik,et al.  Measurements of transient response on lossy microstrips with small dimensions , 1990 .

[4]  William Weigler,et al.  Switching noise in a medium-film copper/polyimide multichip module , 1991 .

[5]  J. Lohstroh Static and dynamic noise margins of logic circuits , 1979 .

[6]  E. H. Fooks,et al.  Microwave engineering using microstrip circuits , 1990 .

[7]  Mani Soma,et al.  Crosstalk analysis of interconnection lines and packages in high-speed integrated circuits , 1990 .

[8]  G.A. Katopis,et al.  Delta-I noise specification for a high-performance computing machine , 1985, Proceedings of the IEEE.

[9]  Stephen I. Long,et al.  Gallium arsenide digital integrated circuit design , 1990 .

[10]  J. L. Prince,et al.  Simultaneous switching ground noise calculation for packaged CMOS devices , 1991 .

[11]  James E. Buchanan Bicmos/cmos Systems Design , 1991 .

[12]  Paul D. Franzon,et al.  Tools to aid in wiring rule generation for high speed interconnects , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[13]  C. S. Chang Electrical design of signal lines for multilayer printed circuit boards , 1988 .

[14]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[15]  A. J. Rainal Computing inductive noise of chip packages , 1984, AT&T Bell Laboratories Technical Journal.

[16]  Tatsuo Itoh,et al.  Planar transmission line structures , 1987 .