Buffer capacity computation for throughput-constrained modal task graphs
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[1] Shuvra S. Bhattacharyya,et al. Parameterized dataflow modeling of DSP systems , 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).
[2] Yongxin Zhu,et al. Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs , 2004, CODES+ISSS.
[3] Lothar Thiele,et al. Complex task activation schemes in system level performance analysis , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[4] Jean A. Peperstraete,et al. Cycle-static dataflow , 1996, IEEE Trans. Signal Process..
[5] Gerard J. M. Smit,et al. Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[6] Clifford Stein,et al. Introduction to Algorithms, 2nd edition. , 2001 .
[7] Anujan Varma,et al. Latency-rate servers: a general model for analysis of traffic scheduling algorithms , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.
[8] Shuvra S. Bhattacharyya,et al. Modeling image processing systems with homogeneous parameterized dataflow graphs , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..
[9] Edward A. Lee,et al. Hierarchical finite state machines with multiple concurrency models , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Edward A. Lee,et al. Dataflow process networks , 1995, Proc. IEEE.
[11] John N. Tsitsiklis,et al. Introduction to linear optimization , 1997, Athena scientific optimization and computation series.
[12] Rolf Ernst,et al. Performance analysis for complex embedded applications , 2005, Int. J. Embed. Syst..
[13] Gerard J. M. Smit,et al. Efficient Computation of Buffer Capacities for Cyclo-Static Real-Time Systems with Back-Pressure , 2006, 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07).
[14] Orlando Moreira,et al. Self-Timed Scheduling Analysis for Real-Time Applications , 2007, EURASIP J. Adv. Signal Process..
[15] Ronald L. Rivest,et al. Introduction to Algorithms , 1990 .
[16] Edward A. Lee,et al. Hierarchical reconfiguration of dataflow models , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..
[17] Gerard J. M. Smit,et al. Buffer Capacity Computation for Throughput Constrained Streaming Applications with Data-Dependent Inter-Task Communication , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.
[18] Richard Kreckel,et al. Introduction to the GiNaC Framework for Symbolic Computation within the C++ Programming Language , 2000, J. Symb. Comput..
[19] Edward A. Lee. Consistency in Dataflow Graphs , 1991, IEEE Trans. Parallel Distributed Syst..
[20] Edward A. Lee,et al. Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[21] Rudy Lauwereins,et al. Cyclo-dynamic dataflow , 1996, Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing.
[22] Guang R. Gao,et al. Well-behaved dataflow programs for DSP computation , 1992, [Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[23] Sander Stuijk,et al. Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs , 2008, IEEE Transactions on Computers.
[24] Heinrich Meyr,et al. Dynamic data flow and control flow in high level DSP code synthesis , 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.
[25] Gerard J. M. Smit,et al. Modelling run-time arbitration by latency-rate servers in dataflow graphs , 2007, SCOPES '07.
[26] Anujan Varma,et al. Latency-rate servers: a general model for analysis of traffic scheduling algorithms , 1998, TNET.
[27] Shuvra S. Bhattacharyya,et al. Consistency Analysis of Reconfigurable Dataflow Specifications , 2002, Embedded Processor Design Challenges.
[28] Yongxin Zhu,et al. Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..