Structural Test Generation for Embedded Analog Macros

|A methodology for structural fault-model based test generation for embedded analog macros in mixed-signal ICs is presented. From the IC-level, parameters reeecting the testability limitations faced by an analog macro under test (MUT) due to surrounding macros are extracted. This method is also suited for quantifying testability reduction and identiication of eecient test insertion points. The parameters are used as integrated part of a structural generation method for compact test sets for analog macros, which deals with the macro at transistor level.