A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning

In this paper, we propose a novel hybrid verification framework (HVF) which uses Reinforcement Learning (RL) and Deep Neural Networks (DNNs) to accelerate the verification of complex systems. More precisely, our HVF incorporates RL to generate all possible sequences of vectors needed to approach a target state as well as the corresponding path to the target state which contains a potential design error. Furthermore, HVF utilizes DNNs to accelerate the verification of complex data paths in the target states. We have tested our framework on several circuits including multi-core designs as well as bus-arbiters and confirmed its significant verification speedup when compared to prior work. For example, HVF provides a total speedup of 4.5x for a quad-core MIPS processor verification.

[1]  William K. Lam Hardware Design Verification: Simulation and Formal Method-Based Approaches (Prentice Hall Modern Semiconductor Design Series) , 2005 .

[2]  László Monostori,et al.  Reinforcement learning for solving shortest-path and dynamic scheduling problems , 2001 .

[3]  Enrico Macii,et al.  Markovian analysis of large finite state machines , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Benjamin C. Lee,et al.  Navigating heterogeneous processors with market mechanisms , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[5]  Kerstin Eder,et al.  Coverage-Directed Test Generation Automated by Machine Learning -- A Review , 2012, ACM Trans. Design Autom. Electr. Syst..

[6]  Shahin Nazarian,et al.  Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework , 2018, ACM Great Lakes Symposium on VLSI.

[7]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[8]  Zeljko Zilic,et al.  Enabling efficient post-silicon debug by clustering of hardware-assertions , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[9]  Shahin Nazarian,et al.  Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).