Digital Adaptive Calibration of Data Converters Using Independent Component Analysis
暂无分享,去创建一个
[1] Rinaldo Castello,et al. A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[2] Chung-Ming Huang,et al. A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[3] Hung-Chih Liu,et al. A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[4] Wenbo Liu,et al. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration , 2011, IEEE Journal of Solid-State Circuits.
[5] Gabor C. Temes,et al. Adaptive compensation of analog circuit imperfections for cascaded delta-sigma ADCs , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[6] Robert W. Brodersen,et al. Background ADC calibration in digital domain , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[7] Seung-Chul Lee,et al. A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR , 2014, IEEE Journal of Solid-State Circuits.
[8] Li Ding,et al. A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
[9] Stephen H. Lewis,et al. Convergence analysis of a background interstage gain calibration technique for pipelined ADCs , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[10] Wenbo Liu,et al. A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.
[11] G.C. Temes,et al. Adaptive compensation of analog circuit imperfections for cascaded /spl Sigma//spl Delta/ modulators , 1996, Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers.
[12] Gilles Burel,et al. Blind separation of sources: A nonlinear neural algorithm , 1992, Neural Networks.
[13] Tai-Cheng Lee,et al. A Split-Based Digital Background Calibration Technique in Pipelined ADCs , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[14] H. S. Fetterman,et al. CMOS pipelined ADC employing dither to improve linearity , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
[15] Un-Ku Moon,et al. "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC , 2006, IEEE Journal of Solid-State Circuits.
[16] S. Haykin,et al. Adaptive Filter Theory , 1986 .
[17] Pierre Comon,et al. Blind separation of sources, part II: Problems statement , 1991, Signal Process..
[18] K. Nair,et al. A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[19] Andrzej Cichocki,et al. Robust neural networks with on-line learning for blind identification and blind separation of sources , 1996 .
[20] P. Hurst,et al. A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.
[21] Christian Jutten,et al. Space or time adaptive signal processing by neural network models , 1987 .
[22] Yun Chiu,et al. Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).
[23] T. Kuyel,et al. A 14 b 40 MSample/s pipelined ADC with DFCA , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[24] Un-Ku Moon,et al. Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection , 2000 .
[25] Borivoje Nikolic,et al. Least mean square adaptive digital background calibration of pipelined analog-to-digital converters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[26] Pierre Comon,et al. Independent component analysis, a survey of some algebraic methods , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[27] I. Galton,et al. A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.
[28] Abhilash Nair,et al. "Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[29] H. B. Barlow,et al. Unsupervised Learning , 1989, Neural Computation.
[30] Yun Chiu. Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
[31] Seung-Chul Lee,et al. Digital Calibration of Nonlinear Memory Errors in Sigma–Delta Modulators , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[32] B. Murmann,et al. A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[33] Seung-Chul Lee,et al. Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[34] Ian Galton,et al. Digital Background Correction of Harmonic Distortion in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[35] Eric A. Vittoz,et al. CMOS Integration of Herault-Jutten Cells for Separation of Sources , 1989, Analog VLSI Implementation of Neural Systems.
[36] Un-Ku Moon,et al. Background calibration techniques for multistage pipelined ADCs with digital redundancy , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[37] Jean-Francois Cardoso,et al. Source separation using higher order moments , 1989, International Conference on Acoustics, Speech, and Signal Processing,.
[38] Craig Petrie,et al. A background calibration technique for multibit delta-sigma modulators , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).
[39] Ian Galton,et al. Gain error correction technique for pipelined analogue-to-digital converters , 2000 .
[40] Ian Galton. Digital cancellation of D/A converter noise in pipelined A/D converters , 2000 .
[41] Shun-ichi Amari,et al. Adaptive blind signal processing-neural network approaches , 1998, Proc. IEEE.
[42] Christian Jutten,et al. Blind separation of sources, part I: An adaptive algorithm based on neuromimetic architecture , 1991, Signal Process..
[43] Yun Chiu,et al. An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.
[44] Esfandiar Sorouchyari,et al. Blind separation of sources, part III: Stability analysis , 1991, Signal Process..
[45] P.G.A. Jespers,et al. A CMOS 13-b cyclic RSD A/D converter , 1992, IEEE Journal of Solid-State Circuits.
[46] Stephen H. Lewis,et al. A 10-b 20-Msample/s analog-to-digital converter , 1992 .
[47] Bang-Sup Song,et al. A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
[48] D.A. Johns,et al. An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage , 2007, IEEE Journal of Solid-State Circuits.
[49] Wenbo Liu,et al. A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[50] M. K. Mayes,et al. A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller , 1996 .
[51] Ian Galton,et al. A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.
[52] E. Oja,et al. Independent Component Analysis , 2013 .