On the Existence of Analytical Proofs for VLSI Computational Networks

In a previous work, it was shown that the verification of a systolic or a deadlock free self timed network may be achieved by solving a system of sequence equations which models the network. Here, we prove that such a system has always a solution which may be expressed in the sequence notation. In particular, the iteration operator is introduced to compensate for the absence of the time dimension from sequence equations, thus providing a suitable notation for the solution of recursive equations resulting from feed back loops.