Trace driven simulation using sampled traces

Trace driven simulation is a well known method for evaluating computer architecture options and is the technique of choice in most published cache and memory studies. Ideally, a trace should contain all the necessary events generated by a program. However, this is usually impractical for all but the most trivial of programs because of trace storage and simulation time costs. As computer systems increase in performance and complexity there is a growing need to use larger and more realistic programs for trace driven simulation. This has lead to a growing interest in applying sampling techniques to reduce trace driven simulation costs. This paper reports on same experiments in trace sampling and discusses a prediction method for resolving cold-start or fill references when simulating with a sampled trace. The paper shows how a small sampled trace can capture the characteristics of a much larger trace and cache simulations results are presented using these sampled traces and the prediction method.<<ETX>>

[1]  A. Dain Samples,et al.  Mache: no-loss trace compaction , 1989, SIGMETRICS '89.

[2]  Wen-Hann Wang,et al.  Efficient trace-driven simulation methods for cache performance analysis , 1991, TOCS.

[3]  Malcolm C. Easton,et al.  Computation of Cold-Start Miss Ratios , 1978, IEEE Transactions on Computers.

[4]  Geoffrey C. Fox,et al.  The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers , 1989, Int. J. High Perform. Comput. Appl..

[5]  Jih-Kwon Peir,et al.  Sampling of cache congruence classes , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[6]  Janak H. Patel,et al.  Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems , 1988, IEEE Trans. Computers.

[7]  Alan Jay Smith,et al.  Two Methods for the Efficient Analysis of Memory Address Trace Data , 1977, IEEE Transactions on Software Engineering.

[8]  Douglas W. Clark,et al.  Measuring VAX 8800 performance with a histogram hardware monitor , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[9]  Janak H. Patel,et al.  How to Simulate 100 Billion References Cheaply , 1991 .

[10]  Susan J. Eggers,et al.  Techniques for efficient inline tracing on a shared-memory multiprocessor , 1990, SIGMETRICS '90.

[11]  W. Kent Fuchs,et al.  TRAPEDS: producing traces for multicomputers via execution driven simulation , 1989, SIGMETRICS '89.

[12]  Ravishankar K. Iyer,et al.  Performance prediction and tuning on a multiprocessor , 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

[13]  David W. Wall,et al.  Generation and analysis of very long address traces , 1990, ISCA '90.

[14]  Alan Jay Smith,et al.  Evaluating Associativity in CPU Caches , 1989, IEEE Trans. Computers.

[15]  Thomas Roberts Puzak,et al.  Analysis of cache replacement-algorithms , 1985 .

[16]  K. So,et al.  Cache performance of vector processors , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.