Ferroelectric memory based secure dynamically programmable gate array

A nonvolatile ferroelectric SRAM based 8-context dynamically programmable gate array enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories. Read and program procedures of the associated configuration memory are securely protected, so that unauthorized users cannot gain access to configuration data. The ferroelectric SRAM configuration memory features 2ns nondestructive read operations along with stable data recall. The logic block circuit is optimized to improve available logic gates for multi-context scheme.

[1]  Noriyuki Suzuki,et al.  A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture , 1992 .

[2]  N. Kasai,et al.  A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[3]  A. Sheikholeslami,et al.  A survey of circuit innovations in ferroelectric random-access memories , 2000, Proceedings of the IEEE.

[4]  André DeHon Entropy, Counting, and Programmable Interconnect , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[5]  P. Chow,et al.  The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Steven Trimberger,et al.  Scheduling designs into a time-multiplexed FPGA , 1998, FPGA '98.

[7]  T. Eshita,et al.  4 Mbit embedded FRAM for high performance System on Chip (SoC) with large switching charge, reliable retention and high imprint resistance , 2002, Digest. International Electron Devices Meeting,.

[8]  J. Rodriguez,et al.  Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process , 2002, Digest. International Electron Devices Meeting,.

[9]  Michael Bolotski Andr,et al.  Unifying FPGAs and SIMD Arrays , 1994 .

[10]  K. Wakabayashi,et al.  A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[11]  S. Kawashima,et al.  Bitline GND sensing technique for low-voltage operation FeRAM , 2002 .

[12]  H. Honda,et al.  A 500 MHz pipelined burst SRAM with improved SER immunity , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[13]  Steven Trimberger,et al.  A time-multiplexed FPGA , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[14]  Ali Sheikholeslami,et al.  A 16 kb 1T1C FeRAM test chip using current-based reference scheme , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[15]  D.D. Buss Technology in the Internet age , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[16]  Motomura,et al.  An Embedded DRAM-FPGA Chip With Instantaneous Logic Reconfiguration , 1997 .