Monitoring Setup and Hold Timing Limits

For safety or AVS applications purpose, it is important to validate and to monitor that the digital circuit is never used outside its worst-case scenario for which it has been designed. Indeed, as there are many sources of static and dynamic variations (process, temperature, local mismatch, aging …), timing closure is performed to fulfil the functionality at best case and worst-case corners. In-Situ Monitor approach are known to be good candidate to rise pre-error flag when circuit operation point is very close to sign-off limits for setup time violations. Here a new validation of this approach is proposed for hold time violations. Implemented on an AES circuit, different experimental characterizations are presented and comparison with Timing Analysis and SPICE simulation are given to illustrate the capability of the approach to detect setup and hold time violation limits. Ageing of circuit exhibits some variation in time of these limits. Finally, different use-case that can affect the hold time violation are presented, and as function of the activity scenario, the slack for the path is discussed.