Timing-Aware Routing in the RapidWright Framework

We can extract approximate, fine-grained timing information of routing resources of Xilinx FPGAs using the RapidWright open-source framework. The absence of timing information makes it difficult to implement timing-aware FPGA CAD tools using RapidWright. It is impractical to invoke Vivado's timing analysis engine for each choice within an optimization loop of your custom CAD algorithm as that would slow down execution by orders of magnitude. We route a set of one-time calibration tests on the FPGA using Vivado to extract path delays, and setup a system of linear equations based on the unknown delays associated with each routing resource used in the calibration route. We run this calibration for an interconnect tile but generalize the result to the entire FPGA due to device symmetry. We then solve these equations using least squares approximation as the resulting system is low-rank. This is due to the routing restrictions imposed by the FPGA fabric for legality of the connection and correctness of Vivado's timing analysis. We are able to learn an approximate timing model for RapidWright that is within 1% error (0.01ns) of Vivado timing analysis by running ?30 calibration runs and needing under 60 seconds of Vivado timing analysis. We demonstrate this technique on Xilinx XCKU115 FPGA (-3, -2, and -1 speed grades). The open-source RapidRoute custom router previously lost to Vivado by as much as 0.3–0.4 ns on timing slack when using a crude timing model. With our timing model enhancements, we allow RapidRoute to close the slack gap with Vivado and even outperform Vivado marginally on occasion. Our timing model generation is lightweight and can be discovered for each FPGA device instead of bundling memory-hungry timing libraries with RapidWright.