论文信息 - Block and track method for automated layout generation of MOS-LSI arrays

Block and track method for automated layout generation of MOS-LSI arrays

An automated layout program with a block and track concept will be described. The program, which takes logic descriptions, can generate composite-patterns for single-chip calculator MOS-LSI arrays within 600 seconds computing time with manual-comparable chip areas.

Tokinori Kozawa | K. Watanabe | H. Horino | M. Nagata | H. Hukuda

[1] D. Schweikert. Computer-generated IGFET layout using a vertically-packed weinberger arrangement , 1971 .

[2] C. Y. Lee. An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..