Learning on an analog VLSI neural network chip

The issues associated with implementing the error backpropagation algorithm on a 64-neuron nonvolatile analog VLSI neural network chip (ETANN) are described. Imperfections in the analog ETANN chip were identified and found to impose constraints on the learning process. A chip-in-the-loop learning technique and an adaptive, reinforced, bake-train-bake scheme are reported. These techniques have shown potential in surmounting the difficulties connected with learning on an analog neural network chip. Experimental results are reported.<<ETX>>