Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertion

For pt. III see ibid., vol. 50, p. 1081-93 (2003). Using a new physical model for the transient response of a distributed resistance-inductance-capacitance (RLC) interconnect with a capacitive load, novel compact expressions have been derived for the 1) time delay, 2) peak crosstalk for coupled lines, 3) optimum number and size of repeaters, and 4) time delay for repeater-inserted distributed resistance-capacitance (RC) and RLC lines. These new models are used to define a design space that illustrates the tradeoff between the number of repeaters and wire cross-section for specified delay and crosstalk constraints.

[1]  F.-Y. Chang.  Transient simulation of nonuniform coupled lossy transmission lines characterized with frequency-dependent parameters. II. Discrete-time analysis , 1992 .

[2]  K. Banerjee,et al.  Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[3]  F.-Y. Chang.  Transient simulation of nonuniform coupled lossy transmission lines characterized with frequency-dependent parameters. I. Waveform relaxation analysis , 1992 .

[4]  Jin Zong,et al.  First-generation MAJC dual microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Yu Cao,et al.  A new analytical delay and noise model for on-chip RLC interconnect , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[6]  William H. Press,et al.  Numerical recipes in C , 2002 .

[7]  Jacob K. White,et al.  Efficient frequency-domain modeling and circuit simulation of transmission lines , 1994 .

[8]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .

[9]  Raguraman Venkatesan.  Multilevel interconnect architectures for gigascale integration (GSI) , 2003 .

[10]  Kaustav Banerjee,et al.  Analysis of on-chip inductance effects for distributed RLC interconnects , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Jose E. Schutt-Aine,et al.  Optimal transient simulation of transmission lines , 1996 .

[12]  Ronald A. Rohrer,et al.  Interconnect simulation with asymptotic waveform evaluation (AWE) , 1992 .

[13]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[14]  A. Richard Newton,et al.  Algorithms for the transient simulation of lossy interconnect , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  James D. Meindl,et al.  Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .

[16]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[17]  F.E. Anderson,et al.  The core clock system on the next generation Itanium/spl trade/ microprocessor , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[18]  James D. Meindl,et al.  Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load termination , 2003 .

[19]  James D. Meindl,et al.  Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions , 2000 .