An Efficient Hardware Architecture for Route Discovery in AODV for a Sensor Node

Internet of Things (IoT) provides an effective way of interacting and exchanging data among a mesh of devices. Low power and high-performance wireless sensor networks permit flexible modeling of IoT. MANETs predominantly deploy Ad-hoc on-demand distance vector (AODV) routing algorithm to develop routes reactively. AODV deploys the destination sequence number by which it provides loop-free routes. In this paper, the hardware architecture for the functionality of the route discovery process utilized in AODV routing protocol is modeled and implemented using Verilog hardware description language and synthesized in XC4VLX25 device. Moreover, some parameter constants have also been taken into consideration to implement a route discovery mechanism for the real-time scenario. The implemented results show that the proposed architecture offers good performance in terms of area, speed and power dissipation.