Fast spiking neural network architecture for low-cost FPGA devices

Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by artificial SNN, the number of required neurons is very high (thousands). In this work, we propose a SNN architecture able to adapt big size networks using reduced hardware resources. While spikes are processed at 1ms time, inter spike time is used for internal calculations, a mixed serial-parallel structure allows optimized computation of all neuron output values. Results show that SNN can be accommodated using a medium-size FPGA device such as Xilinx Spartan 3 with processing speed comparable to fully parallel implementations with up to 70% resource reduction.

[1]  Matti Tommiska,et al.  Efficient digital implementation of the sigmoid function for reprogrammable logic , 2003 .

[2]  Alfredo Rosado-Muñoz,et al.  FPGA implementation of Spiking Neural Networks supported by a Software Design Environment , 2011 .

[3]  Gert Cauwenberghs,et al.  Saliency-driven image acuity modulation on a reconfigurable silicon array of spiking neurons , 2004, NIPS 2004.

[4]  Wulfram Gerstner,et al.  SPIKING NEURON MODELS Single Neurons , Populations , Plasticity , 2002 .

[5]  Simei Gomes Wysoski,et al.  Fast and adaptive network of spiking neurons for multi-view visual pattern recognition , 2008, Neurocomputing.

[6]  Murray Shanahan,et al.  Training a spiking neural network to control a 4-DoF robotic arm based on Spike Timing-Dependent Plasticity , 2010, The 2010 International Joint Conference on Neural Networks (IJCNN).

[7]  Hani Hagras,et al.  Evolving spiking neural network controllers for autonomous robots , 2004, IEEE International Conference on Robotics and Automation, 2004. Proceedings. ICRA '04. 2004.

[8]  Laurent Perrinet.  Sparse spike coding : applications of neuroscience to the processing of natural images , 2008, SPIE Photonics Europe.

[9]  Abdelkader Benyettou,et al.  Image clustering with spiking neuron network , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[10]  Sander M. Bohte,et al.  Computing with Spiking Neuron Networks , 2012, Handbook of Natural Computing.

[11]  Dario Floreano,et al.  Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot , 2003, NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings..

[12]  Andreas G. Andreou,et al.  Distortion of Neural Signals by Spike Coding , 2007, Neural Computation.

[13]  Dario Floreano,et al.  Evolution of Spiking Neural Controllers for Autonomous Vision-Based Robots , 2001, EvoRobots.

[14]  Olaf Booij,et al.  Temporal Pattern Classification using Spiking Neural Networks , 2004 .

[15]  Qingxiang Wu,et al.  Processing visual stimuli using hierarchical spiking neural networks , 2008, Neurocomputing.

[16]  Manuel Bataller-Mompeán,et al.  FPGA Implementation of Spiking Neural Network , 2012, CESCIT.

[17]  Bernabé Linares-Barranco,et al.  Fast Vision Through Frameless Event-Based Sensing and Convolutional Processing: Application to Texture Recognition , 2010, IEEE Transactions on Neural Networks.

[18]  F. Rattay,et al.  The handbook of brain theory and neural networks , 1996 .

[19]  Yongji Wang,et al.  Corridor-Scene Classification for Mobile Robot Using Spiking Neurons , 2008, 2008 Fourth International Conference on Natural Computation.