Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

Leakage power has already been consuming a considerable portion of the active power in recent process technologies. In this chapter, we survey various power gating techniques to reduce the leakage power of on-chip routers. Then we introduce a run-time fine-grained power-gating router, in which power supply to each router component (e.g., virtual-channel buffer, crossbar’s multiplexer, and output latch) can be individually controlled in response to the applied workload. The fine-grained power gating router with 35 micro-power domains is designed using a commercial 65 nm process and evaluated in terms of the area overhead, application performance, and leakage power reduction.

[1]  Kenji Hirose,et al.  A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones , 2005, IEICE Trans. Electron..

[2]  Simon W. Moore,et al.  Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[3]  Milo M. K. Martin,et al.  Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.

[4]  Hideharu Amano,et al.  Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks , 2008 .

[5]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[6]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[7]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[8]  Li Shang,et al.  Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[9]  T. Hattori,et al.  Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[10]  Li-Shiuan Peh,et al.  Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks , 2007, IEEE Transactions on Parallel and Distributed Systems.

[11]  Hiroshi Nakamura,et al.  A fine-grain dynamic sleep control scheme in MIPS R3000 , 2008, 2008 IEEE International Conference on Computer Design.

[12]  Hideharu Amano,et al.  Prediction router: Yet another low latency on-chip router architecture , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[13]  Y. Kojima,et al.  Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[14]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[15]  Hideharu Amano,et al.  Run-time power gating of on-chip routers using look-ahead routing , 2008, 2008 Asia and South Pacific Design Automation Conference.

[16]  Doug Burger,et al.  An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches , 2002, ASPLOS X.

[17]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[18]  Pradip Bose,et al.  Microarchitectural techniques for power gating of execution units , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[19]  Milo M. K. Martin,et al.  Token Coherence: decoupling performance and correctness , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[20]  Nicholas P. Carter,et al.  Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction , 2004, IEEE Computer Architecture Letters.

[21]  Arnab Banerjee,et al.  A Power and Energy Exploration of Network-on-Chip Architectures , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[22]  Mike Galles.  Spider: a high-speed network interconnect , 1997, IEEE Micro.

[23]  Fabien Clermidy,et al.  An asynchronous power aware and adaptive NoC based circuit , 2008, 2008 IEEE Symposium on VLSI Circuits.

[24]  Kimiyoshi Usami,et al.  A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals , 2006, 2006 International Conference on Computer Design.