The effect of deep trench and sub-collector on the latchup robustness in BiCMOS silicon germanium technology

This paper demonstrates the influence and improvement of deep trench (DT) isolation, and bipolar sub-collector on CMOS latchup in a 0.13 /spl mu/m CMOS-based 200/285 GHz (f/sub T//f/sub max/) SiGe HBT technology.

[1]  A. Watson,et al.  The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[2]  Donald B. Estreich.  The physics and modeling of latch-up and CMOS integrated circuits , 1980 .

[3]  Ronald R. Troutman.  Latchup in CMOS Technology , 1986 .

[4]  Steven H. Voldman,et al.  MeV implants boost device design , 1995 .

[5]  W. Morris,et al.  Latchup in CMOS , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[6]  A. Ochoa,et al.  An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process , 1978, 1978 International Electron Devices Meeting.