A Wavefront Notation Tool for VLSI Array Design

This paper presents an overview of an extension to a mathematically based methodology for mapping an algorithmic description into a concurrent implementation on silicon. The result of this methodology yields a systolic array [4]. The basic mathematical method was initially described by Cohen [1]. Extensions were made by Weiser and Davis [5]; Johnsson, Weiser, Cohen, and Davis [2]; Cohen and Johnsson [3]; and Weiser [6]. This approach focuses on the correspondence between equations defining a certain computation and networks which perform the computation. As the complexity of problems increases, a hierarchical approach can reduce the complexity by hiding detail and thus reduce the design complexity at each level. The purpose of this paper is to introduce a method for treating sets of data as wavefront entities in the equations of the mathematical methodology and in the graphical representation.