For next generation image compression standard, context-based arithmetic coding is adopted for improving the compression rate. An efficient and high throughput codec design is strongly required for handling high-resolution images. We propose an efficient codec architecture for context-based adaptive arithmetic coding, which exhibits low cost, low latency, and high throughput rate. In addition, it can be programmed for supporting multiple standards such as JPEG, JPEG2000, JBIG, and JBIG2 standards. It exploits three-pipeline stages architecture. Based on parallel leading zeros detection and bit-stuffing handling, symbols can be encoded and decoded within one cycle. Therefore, the throughput rate can be increased as high as the codec operating clock rate. For 0.35 /spl mu/ 1P4M CMOS technology, both the encoding and decoding rate can run up to 185 M symbol/sec. The AC codec only costs 12 K gate count and 860 /spl mu/m/spl times/860 /spl mu/m layout area. These performances can meet high-resolution real time application requirements.
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