Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits

This paper will show developing a system-on-chip (SoC) synthesis tool which is able to automatically generate a set of analog blocks. Our approach leverages a differentiating technology to automatically synthesize “correct-by-construction” Verilog descriptions for both analog and digital circuits and enable a portable, single pass implementation flow. The SoC synthesis tool realizes analog circuits, including phase locked loops (PLL), power management, analog to digital converters (ADC), and sensor interfaces by recasting them as structures composed largely of digital components while maintaining analog performance. They are then expressed as synthesizable Verilog blocks composed of digital standard cells augmented with a few auxiliary cells generated with an automatic cell generation tool. By expanding the IPXACT format and the Socrates tool from ARM, we then enable composition of vast numbers of digital and analog components into a single correct-by-construction design. Keywords— Automatic synthesis tool; SoC; Synthesizable analog block; IPXACT; Differentiating technology