Comparative analysis of 8 X 8 Bit Vedic and Booth Multiplier

Speed and power consumption are one of the most important parameters to judge the performance of a computational method. In this paper, we compare two algorithms for 8 Bit multiplication namely Vedic Multiplication Algorithm and Booth algorithm. This paper aims in bringing to the fore the differences in compilation speeds and the chip area consumption of the two methodologies. The programming language used is Verilog and the synthesis has been done on Xilinx 14.5.