An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

An 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13/spl mu/m CMOS. The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

[1]  John G. Proakis,et al.  Digital Communications , 1983 .

[2]  R. Mooney,et al.  A 900 Mb/s bidirectional signaling scheme , 1995 .

[3]  M. Horowitz,et al.  A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating range , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[4]  James E. Jaussi,et al.  An 8-Gb/s simultaneous bidirectional link with on-die waveform capture , 2003, IEEE J. Solid State Circuits.

[5]  Gu-Yeon Wei,et al.  An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS , 2003 .

[6]  David J. Comer,et al.  A High-Frequency CMOS Current Summing Circuit , 2003 .

[7]  R. Mooney,et al.  8Gb/s differential simultaneous bidirectional link with 4mV 9ps waveform capture diagnostic capability , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[8]  R. Mooney,et al.  Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 /spl mu/m CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[9]  T. Lee,et al.  A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[10]  Behzad Razavi,et al.  A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).